Rustamji Institute of Technology

Dr. Anjana Goen
Associate Professor
Department of Electronics & Communications
Email: anjana@rjit.org
Mobile: 9425755052
Address: Department of Electronics & Communication Engineering RJIT-BSF Academy, Tekanpur- 475005
Experience: 25 Years
Date of Joining: 15-04-2000
Education & Qualification:

  • MTech (Telecomm ( Biomedical Signal and Image Processing, Digita) from MITS, Gwalior in 2012
  • Ph.D. (Digital Signal and Image Processing) from Jiwaji University, Gwalior in 2015

Membership of Professional Bodies:
  • Annual Member of Indian Society of Technical Education: 2006-07
  • Life Member of the Institute of Electronics & Telecommunication Engineering: M-135716
  • Life Member of the Institute of Engineers (India): M-15-2126-2
Achievements/Awards:
  • Commendation Card by IG/Director, BSF Academy, Tekanpur
  • Certificate for Excellent contribution as Reviewer Biomedical and Pharmacology Journal
Projects Undertaken:
  • Implementation of a Novel technique for Steganography with Enhanced LSB by Asheesh Shrivastava” in 2019
  • Energy conservation through Hybrid Algorithm to Increase the lifetime of Wireless Sensor Networks by “Dheeraj Singh Tomar” in 2019
  • Design and Implementation of Smart Home Security System using GSM Technology by “Aman Sharma” in 2019
  • Design & Implementation of Smart Traffic Control System using Weighted Data and RFID by “Priyanka Sharma” in 2019
  • Design and analysis of Microstrip Low Pass filter for WIFI Applications by “Aanshi Jain” in 2018
  • Implementation of Articulation point technique into MCDS based routing in MANET by “Neetendra Singh Dhakad” in 2017
  • Design and Characterization of Microstrip patch Antenna for WLAN and WI-MAX Application by “Meenal Kate” in 2016
Activities Organized:
Academic/Administrative Works:
  • Head of Information Technology Department
    Working Duration: 02 years
  • Girls Hostel Committee
    Working Duration: 5 Years
  • Head Academics
    Working Duration: 01 Year
  • Head of Electronics Engineering Department
    Working Duration: 11 Years
FDP/STTP Attended:
Publications (International):
S.No. Title of Publication Journal Month-Year of Publicaiton ISSN No. of Co-Authors
1FPGA Based Digital Phase Locked Loop using VHDL CodingInternational Journal of Engineering Research and Applications (IJERA) International Journal of Engineering Research and Applications (IJERA) Vol. 10, Issue 7, (Series-III)Jul-20202248-96221
2Reduce & Compare PAPR Noise with Selecting Mapping & Partial Transmission Sequence using OFDMInternational Journal of Engineering Research and Applications, Vol. 10, Issue 5, (Series-IV)May-20202248-96221
Publications (National): No National Publication